As shown in FIG. 1, magnetic recording devices, such as hard disk drives (referred to below as HDD), etc., are generally tested by writing data signals to be recorded on a disk 103 to be tested, through recording amplifier 101 and recording head 102. Thereafter, the data that has been written is read as regenerated signals through regeneration head 104 and regeneration amplifier 105, and these data are compared with the signals to be recorded. However, the peak position of the regeneration signals is displaced from the polarity transition point (transition) of the signals to be recorded due to the nonlinearity of this magnetic conversion system in magnetic recording devices, such as HDD, etc., (in other words, NLTS) Accordingly, the signals to be recorded must be corrected in order to cancel this phenomenon.
This phenomenon has been recognized as a significant factor that prevents from increasing the recording density of magnetic recording devices, such as HDD in particular. For instance, FIG. 2 shows the waveform of the signals to be recorded and the waveform of regeneration signals in the recording and regeneration system of the HDD of FIG. 1. Since the polarity transition distance of the signals to be recorded is relatively narrow between transitions C-D, adjacent transitions interfere with one another, resulting in NLTS. In this embodiment, the distance between the peaks of the regeneration signals is employed. On the other hand, the polarity transition distance between transitions A-B is relatively broad, and therefore, there is little interference between adjacent transitions and almost no NLTS is produced.
The NLTS correction circuit, which corrects the data to be recorded to cancel the NLTS that is expected during signal recording, is a well-known means for solving the problem. This NLTS correction circuit comprises a data pattern analyzer for analyzing the pattern of data to be recorded, which is designed in accordance with a prescribed table for converting the NLTS correction value for the pattern of data to be recorded. The data pattern analyzer estimates the amount and direction of NLTS produced between transitions C-D. This NLTS pre-corrects the signals to be recorded so that transitions C and D which include desired peak distance on regenerated signal at the bottom of FIG. 3 are obtained.
The table for converting the NLTS correction value of the data pattern will be explained hereafter. NLTS correction of HDD is usually performed based on intermediate data, which are converted from data to be recorded before they are recorded. There are various methods of accomplishing this conversion, an explanation will be made here by taking the intermediate data as an example that takes 1 in case there is a logical change in a bit value of a recording signal from its immediately preceding bit value and takes 0 in case there is no change. That is, the signals to be recorded are reversed when the logic of the intermediate data is 1. For instance, when part of a series of intermediate data is "10100110", the corresponding data to be recorded become "11000100," as shown in FIG. 2. Since transient shift is caused by the interference between contiguous logic is in the in termediate data to be recorded, it is understood that NLTS tends to happen at transients C and D in FIG. 2. In contrast, the amount of interference between the two transitions decreases as the distance between the transitions increases. Thus, assuming that the range in which the effect of the interference cannot be ignored is, for example, both the preceding and succeeding two bits of a transition, a table of "Data pattern-NLTS correction value" as shown in Table 1 is obtained in accordance with the above-described principle, by treating the combination of the data bit that is about to be recorded and its preceding two bits and succeeding two bits as one data pattern of five bits, and correlating each possible data pattern with its NLTS correction value. Only data patterns where the bit exactly in the middle is 1 can be treated by using this type of system and therefore, the number of rows in the table is reduced by half and the table is efficient. The amount of each NLTS correction varies with the characteristic of the recording medium that is the subject of the measurements and is determined by measuring the NLTS produced in regenerated signals with an HDD tester. Furthermore, the number of the delay line that should be selected for each data pattern is easily determined using the "NLTS Correction Value-Delay Line Number Table" (Table 2), which defines the number of the delay line that should be selected for each NLTS correction value. The data pattern analyzer operates in accordance with the "Data Pattern-NLTS Correction Value Table" and "NLTS Correction Value-Delay Line Number Table" obtained in this way.
TABLE 1 ______________________________________ Data Pattern-NLTS Correction Value Table NLTS correction value (+ indicates delayed correction, indicates advanced Data pattern correction) ______________________________________ 00100 0 00101 +100 ps 00110 +200 ps 00111 +220 ps 01100 -200 ps 01101 -150 ps 01110 0 01111 0 10100 -100 ps 10101 0 10110 +150 ps 10111 +100 ps 11101 -100 ps 11100 -220 ps 11110 0 11111 0 ______________________________________
TABLE 2 ______________________________________ NLTS Correction Value/Delay Line Number Table NLTS correction value Delay line number ______________________________________ -220 ps 0 -200 ps 1 -150 ps 2 -100 ps 3 0 4 +100 ps 5 +150 ps 6 +200 ps 7 +220 ps 8 ______________________________________
Data recording devices usually have a data buffer memory 401 (FIG. 4) for conversion of the nonsynchronized record data signals to be recorded from the host computer to signals having the data rate of the recording channel. Data that have been stored in data buffer memory 401 are read at a predetermined channel data rate from the channel clock and recorded on the medium by recording head 102 through recording amplifier 101.
FIG. 5 shows an example of NLTS correction circuit 500 of the prior art. This correction circuit of the prior art which is disposed between data buffer memories 401 and recording amplifier 101. This conventional NLTS correction circuit 500 comprises several delay lines DL.sub.0 -DL.sub.2, a selector 502, which selectively switches the output of the delay lines, and a data pattern analyzer 503, which controls the selector 502. The delay line that delays the current data about to be recorded is selected and NLTS correction is performed for the data based on the analysis results of data pattern analyzer 503. The term "record data pattern" that is used here is defined as a series of numbers which is a section of the intermediate data. Although the way of conversion of the data to be recorded to intermediate data, varies with the HDDs and the HDD testers, for convenience, it is defined in this specification that record data is converted to intermediate data 506 by record data-intermediate data conversion circuit 508 before they are input to the shift register of the data pattern analyzer. Furthermore, the D-type flip-flop represented by reference 509 in FIG. 5 is used to match the timing of the data to be recorded and that of the intermediate data.
Specifically, data pattern analyzer 5.03 comprises shift register 504, which shifts intermediate data 506 for each predetermined channel clock, and decoder 507, which decodes the output from shift register 504. Shift register 504 comprises D-type flip-flops 505, and the number of its stages is determined by the number of preceding and succeeding bits on which the pattern analysis is to be conducted. In FIG. 5, five bits are the subject of the analysis, and there are therefore four stages of flip flops. Decoder 507 produces selector control signals based on a predetermined logic ("Data Pattern-NLTS Correction Value Conversion Table") in accordance with the pattern of the data to be recorded that is input and sends these signals to the selector. The selector control signal select a delay line so that the data signal that is about to be recorded may be corrected with the optimal delay.
The conventional method of correcting data to be recorded will be described while referring to the simple example in FIG. 5.
The intermediate data are shifted sequentially through shift register 504, which has four flip-flops 505, in response to the channel clocks. The logical output of each flip-flop in the shift register is named F(-2) . . . F(2) (provided that F(2) is the logical value for the input of the first flip-flop of the first step). F(0) is the intermediate data corresponding to the current data or data about to be recorded. Thus, shift register 504 is arranged such that preceding two bits (logic values F(-2) and F(-1) of the flip-flop) and succeeding two bits (logic values F(1) and F(2) of the flip-flop) exist therein with the current one in the center.
Logical values F(-2) . . . F(2) are input in parallel into decoder 507. The decoder determines whether correction of data about to be recorded D(k) is necessary or not and the direction of the correction (delay/advance and the amount of correction) by monitoring the signals F(-2) through F(2). Then, the decoder transmits selector control signals to the selector so that the delay line through which the D(k) signal about to be recorded passes will be selected in accordance with this amount of correction. FIG. 6 shows data D(k) about to be recorded and its preceding and succeeding data series and a series of intermediate data ID(k) corresponding to it. Correction is needed only for the leading edge transition (the leading edge transition D(k) should be delayed and the leading edge transition D(k+1) should be advanced) and no correction is needed for the rest. In case no correction is needed, the decoder activates switch S1 so that DL.sub.1 will be selected that has the medium delay.
On the first phase correction of transition, which is the leading transition of D(k) in FIG. 6, the value of
{F(-2) . . . F(2)}={ID(k-2), ID(k-1), ID(k), ID(k+1), ID (k+2)}={0, 0, 1, 1, 0} PA1 {F(-2) . . . F(2)}={ID(k-1), ID(k), ID(k+1), ID(k+2), ID (k+3)}={0, 1, 1, 0, 0} PA1 (1) when characteristic of the head and recording medium have changed; PA1 (2) when recording density is changed; PA1 (3) when the conversion table (Table 1) is required to be modified dynamically as a result of changes in the characteristic of the head or recording medium. PA1 (1) It is difficult to produce high-precision delay lines with a precision of .+-.10 Ps at a maximum delay of 400 Ps and a resolution of 20 ps. PA1 (2) When semiconductor delay lines are used, a change in the amount of delay of as much as .+-.10% is unavoidable, depending on the temperature characteristic of the semiconductor. PA1 (3) When passive delay lines are used, stability is much better than with semiconductor delay lines because of changes in temperature, but it is difficult to obtain delay lines with 20 Ps tracks of 400 Ps, 380 Ps, 360 Ps, . . . , 40 Ps, 20 Ps. PA1 (4) Even if problems 1 and 2 are solved, since the (n+1) to 1 selector (shown by reference 502 in FIG. 5) has n+1 input wiring with different positions, the difference in the wiring length within the selector as well as the difference in the length of the wiring in the printed pattern inevitably leads to a difference in delay of several 10 Ps. PA1 (5) When a resolution of 20 Ps is made with a digital counter, the counter clock is calculated on 50 GHz (1/20 Ps 50 GHz), which makes practical use difficult.
is input to the decoder. If the decoder logic is such that S2 is activated when the data pattern "00110" is input, the leading transition of D(k) will pass through DL.sub.2 which has a longer delay time, and D(k) will be recorded as delayed data D(k)'. On the second phase correction of transition, which is the leading transition of D(k+1) in FIG. 6, the value
is input to the decoder. If the decoder logic is such that switch S0 is activated when data pattern "01100" is input, the leading transition of D(k+1) will pass through DL.sub.0, which has a shorter delay time, and D(k+1) will be recorded as data D(k+1)' to which an advancing correction has been applied. Thus, the transition of the signals about to be recorded is corrected by an amount of correction that is selected according to the logical value of the past and future several bits of data.
Data pattern analyzer 503 operates as described above, but logical modification of the number of stages in shift register 504 and decoder 507 is inevitable in the following cases:
As the recording density of the medium is reduced, the NLTS correction value also decreases. For example, the channel clock frequency is constant in conventional technique. Therefore, if the recording medium is a disk, the recording density of outer tracks is lower than that of inner tracks, which requires logic modification for each tracks. With respect to the fluctuations in the characteristics of the heads and the recording media, they are caused by, for heads, the degradation in time and by, for recording media, fluctuations in the maximum recording density in the test where exchanges of different types of media are done and the test where there are variations in the performances of the instances of a type of recording medium. In such cases, the conversion table is required to be modified according to the fluctuations. In particular, when the recording medium is tape, the medium and head are brought into contact with one another by scanning and therefore, the head becomes worn and degradation takes place over time. In case a medium is exchangeable as with a floppy disk, the NLTS characteristics vary depending on the individual medium.
Because the shift register and the decoder are driven at the channel clock rate that is of too high frequency for a CPU to respond to, they are implemented solely with hardware. Thus, modification of the logic becomes difficult. There is a means for changing decoder logic using a PLD (programmable logic device), but because of problems with operating speed, it is necessary to simulate the operating speed of the logic circuit in order that the PLD may be driven at a high-speed data rate. Thus, inexpensive and simple modification of logic is substantially impossible.
Next, with regard to the problem of the precision of NLTS correction in the prior art, first of all, difficulty of establishing NLTS correction precision required by the NLTS correction circuit will be discussed.
In the case of an HDD, the NLTS correction value, when recording density has been increased to its limit, can be regarded as 20% of the channel clock period or less. This is caused by the fact that the regeneration error rate increases and practical use is impossible under a high recording density requiring this much NLTS correction or more. On the other hand, progress has been made in high-speed transfer, with the standard transfer rate being a channel rate of 500 Mbps on the development. Therefore, the precision and resolution of the desired NLTS correction value is calculated as shown in Table 3 below:
TABLE 3 ______________________________________ Desired precision and resolution of the NLTS correction value ______________________________________ Channel clock frequency, fch 500 MHz (channel rate 500 Mbps) Channel period, T 2000 ps (T = 1/500 MHz) Maximum NLTS correction value, 400 ps (2000 ps .times. 20%) Tc.sub.-- max NLTS correction resolution, 20 ps (2000 ps .times. 1%) Tc.sub.-- res Precision of the NLTS correction .+-. 10 ps value, Tc.sub.-- prec ______________________________________
Consequently, the following problems are encountered with NLTS correction precision:
These problems are significant to NLTS measurement. This is because a flexible response to various pattern analysis algorithms and very precise NLTS correction are needed for NLTS instrumentation.
Consequently, an object of the present invention is to realize a circuit for high precision calibration of the amount of delay of each delay line that is used in an NLTS correction circuit and its method.